`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:39:45 04/30/2014 
// Design Name: 
// Module Name:    clk_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clk_div(clkIN, threshold, clkOUT);

	input clkIN;
	input [31:0] threshold;  // threshold = (frequency of clkIN/(2*desired freq))
	output reg clkOUT;
		initial clkOUT<=1'b0;

		///////////////////////////////////////////////////
		// CLK division  //
		///////////////////
			reg[31:0] timer;  // counts up to threshold
				initial timer <= 0;
				
			// clock division:	
			always @ (posedge clkIN)
				begin
					timer <= timer + 1'b1;
					
				if (timer == threshold) 
					begin
						timer <= 0;
						clkOUT <= ~clkOUT;
					end			
				end
		//////////////////////////////////////////////////

endmodule
